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19-2390; Rev 0; 4/02
Lowest Jitter Quad PECL-to-ECL Differential Translators
General Description
The MAX9424-MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps(RMS) random jitter and channel-tochannel skew is less than 90ps in asynchronous mode. The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. The parts differ from one another by their input and output termination options. The input options are an open input or an internal differential 100 termination. The output options are an open-emitter output or a series 50 termination. See Ordering Information. The MAX9424-MAX9427 operate from a positive voltage supply of +2.375V to +5.5V, and a negative supply voltage of -2.375V to -5.5V and operate across the extended temperature range of -40C to +85C. They are offered in 32-pin 5mm x 5mm TQFP and space-saving 5mm x 5mm QFN packages. o 0.24ps RMS Added Random Jitter o 10ps Channel-to-Channel Skew in Synchronous Mode o Guaranteed 500mV Differential Output at 3GHz Clock Frequency o 420ps Propagation Delay in Asynchronous Mode o Functionally Compatible with SK4426 (MAX9424) SK4430 (MAX9425) SK4436 (MAX9426) SK4440 (MAX9427) o Integrated 50 Outputs (MAX9425/MAX9427) o Integrated 100 Inputs (MAX9426/MAX9427) o Synchronous/Asynchronous Operation
Features
MAX9424-MAX9427
Ordering Information
INPUT OUTPUT (IN_, (OUT_, OUT_) IN_) MAX9424EHJ -40C to +85C 32 TQFP Open Open MAX9424EGJ* -40C to +85C 32 QFN Open Open MAX9425EHJ -40C to +85C 32 TQFP Open 50 MAX9425EGJ* -40C to +85C 32 QFN Open 50 MAX9426EHJ -40C to +85C 32 TQFP 100 Open MAX9426EGJ* -40C to +85C 32 QFN 100 Open MAX9427EHJ -40C to +85C 32 TQFP 100 50 MAX9427EGJ* -40C to +85C 32 QFN 100 50 *Future product--contact factory for availability. PART TEMP RANGE PINPACKAGE
Applications
Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE
Pin Configurations
OUT0 OUT0
VGG
TOP VIEW
OUT0 OUT0 VGG VEE IN0 IN0 IN1 IN1
TOP VIEW
IN0 IN0 32 31
VEE
IN1
30
29
28
27
32 VCC SEL SEL CLK CLK EN EN VCC 1 2 3 4 5 6 7 8 9 IN3
31
30
29
28
27
26
25 24 VGG 23 OUT1 22 OUT1
*
26
25
*
IN1
VCC SEL SEL CLK CLK EN EN VCC
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
* *
24 23 22
VGG OUT1 OUT1 VEE VEE OUT2 OUT2 VGG
MAX9424 MAX9425 MAX9426 MAX9427
21 VEE 20 VEE 19 OUT2 18 OUT2 17 VGG
MAX9424 MAX9425 MAX9426 MAX9427
21 20 19 18 17
10 IN3
11 VGG
12 OUT3
13 OUT3
14 VEE
15 IN2
16
9
OUT3
OUT3
VEE
IN2
IN3
IN3
IN2
VGG
TQFP (5mm x 5mm)
QFN
NOTE: CORNER PINS ARE CONNECTED TO VGG.
________________________________________________________________ Maxim Integrated Products
IN2
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
ABSOLUTE MAXIMUM RATINGS
VCC to VGG ............................................................-0.3V to +6.0V VGG to VEE.............................................................-0.3V to +6.0V Input Pins to VGG ........................................-0.3V to (VCC + 0.3V) Differential Input Voltage ..............................|VCC - VGG| or 3.0V, whichever is less Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/C above +70C) .................................761mW 32-Pin 5mm x 5mm QFN (derate 21.3mW/C above +70C) ...................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm x 5mm TQFP ........................................+105C/W 32-Pin 5mm x 5mm QFN............................................+47C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin 5mm x 5mm TQFP ..........................................+73C/W Junction-to-Case Thermal Resistance 32-Pin 5mm x 5mm TQFP ..........................................+25C/W 32-Pin 5mm x 5mm QFN..............................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (all input pins) ...............................500V Human Body Model (all output pins) ...............................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VGG = 2.375V to 5.5V, VGG - VEE = 2.375V to 5.5V, MAX9424/MAX9426 outputs terminated with 50 to VGG - 2.0V, MAX9425/MAX9427 not externally terminated, TA = -40C to +85C. Typical values are at VCC - VGG = 3.3V, VGG - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS MIN VGG + 1.4 VGG VCC - VGG < 3.0V VCC - VGG 3.0V Input Current Differential Input Resistance (IN_, IN_) OUTPUTS (OUT_, OUT_) Differential Output Voltage Output Common-Mode Voltage Output Impedance Internal Current Source POWER SUPPLY Positive Supply Current Negative Supply Current ICC IEE (Note 4) MAX9424/MAX9426 (Note 4) MAX9425/MAX9427 (Note 4) 16 100 172 27 130 230 mA mA VOH - VOL VOCM ROUT ISINK Figure 1 Figure 1 MAX9425/MAX9427 MAX9425/MAX9427 600 VGG 1.50 40 6 635 VGG 1.25 50 8 VGG 1.05 60 10 mV V mA IIH, IIL MAX9424/ MAX9425 MAX9426/ MAX9427 EN, EN, SEL, SEL, IN_, IN_, CLK or CLK = VIHD or VILD EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD 0.2 0.2 -10 -10 86 100 TYP MAX UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage Differential Input Low Voltage VIHD VILD VID Figure 1 Figure 1 VCC VCC 0.2 VCC VGG 3.0 25 A 25 114 V V
Differential Input Voltage
Figure 1
V
RIN
MAX9426/MAX9427
2
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Lowest Jitter Quad PECL-to-ECL Differential Translators
AC ELECTRICAL CHARACTERISTICS
(VCC - VGG = 2.375V to 5.5V, VGG - VEE = 2.375V to 5.5V, outputs terminated with 50 to VGG - 2.0V, EN = VIHD, EN = VILD, fCLK 3.0GHz, fIN 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VGG + 1.4V to VCC, VILD = VGG to VCC - 0.2V, VIHD - VILD = 0.2V to smallest of |VCC - VGG| or 3.0V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC - VGG = 3.3V, VGG - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.) (Notes 1 and 5)
PARAMETER IN_ to OUT_ Differential Propagation Delay CLK to OUT_ Differential Propagation Delay OUT_ to OUT_ Skew OUT_ to OUT_ Skew SYMBOL tPLH1 tPHL1 tPLH2 tPHL2 tSKD1 tSKD2 fCLK(MAX) CONDITIONS Figure 3, SEL = high, asynchronous operation Figure 4, SEL = low, synchronous operation SEL = high, asynchronous operation (Note 6) SEL = low, synchronous operation (Note 6) MAX9424/MAX9426, VOH - VOL 500mV, SEL = low MAX9425/MAX9427, VOH - VOL 300mV, SEL = low MAX9424/MAX9426, VOH - VOL 400mV, SEL = high MAX9425/MAX9427, VOH - VOL 250mV, SEL = high SEL = low, fCLK = 3.0GHz clock, fIN = 1.5GHz (Note 7) SEL = high, fIN = 2.0GHz (Note 7) Added Deterministic Jitter tDJ tS tH tR tF tPD/T SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps 223 - 1 PRBS pattern (Note 7) SEL = high, IN_ = 2.0Gbps 223 - 1 PRBS pattern (Note 7) Figure 4 Figure 4 Figure 3 Figure 3 80 80 89 87 0.2 120 120 1 MIN 300 460 TYP 420 580 38 10 MAX 570 730 90 70 UNITS ps ps ps ps
MAX9424-MAX9427
Maximum Clock Frequency
3.0
GHz
Maximum Data Frequency
fIN(MAX)
2.0
GHz
Added Random Jitter
tRJ
0.24 0.3 27 20
0.8 0.8 80
ps(RMS)
ps(P-P) 80 ps ps ps ps ps/C
IN_ to CLK Setup Time CLK to IN_ Hold Time Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All outputs open, all inputs biased differential high or low except VCC, VGG, and VEE. Note 5: Guaranteed by design and characterization, and are not production tested. Limits are set to 6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Device jitter added to the input signal.
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
Typical Operating Characteristics
(MAX9424: VCC - VGG = 3.3V, VGG - VEE = 3.3V, outputs terminated with 50 to VGG - 2.0V, enabled, fCLK = 3.0GHz, fIN = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9424-MAX9427 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. IN_ FREQUENCY
MAX9424-MAX9427 toc02
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9424-MAX9427 toc03
650 600 OUTPUT AMPLITUDE (mV) SEL = HIGH 550 500 450 400 350
94
100 SUPPLY CURRENT (mA)
IEE
OUTPUT RISE/FALL TIME (ps)
92 FALL TIME 90 RISE TIME 88
75 INPUTS BIASED DIFFERENTIALLY HIGH OR LOW, OUTPUTS OPEN
50
25
ICC
86
0 -40 -15 10 35 60 85 TEMPERATURE (C)
84 0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -15 10 35 60 85 IN_ FREQUENCY (GHz) TEMPERATURE (C)
IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
MAX9424-MAX9427 toc04
CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
CLK-TO-OUT PROPAGATION DELAY (ps)
MAX9424-MAX9427 toc05
420 IN-TO-OUT PROPAGATION DELAY (ps) tPHL1 410
630 620 610 600 590 580 570
400 tPLH1 390
tPLH2, tPHL2
380 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
4
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Lowest Jitter Quad PECL-to-ECL Differential Translators
Pin Description
PIN 1, 8 2 3 4 5 6 7 9 10 11, 17, 24, 30 12 13 14, 20, 21, 27 15 16 18 19 22 23 25 26 28 29 31 32 NAME VCC SEL SEL CLK CLK EN EN IN3 IN3 VGG OUT3 OUT3 VEE IN2 IN2 OUT2 OUT2 OUT1 OUT1 IN1 IN1 OUT0 OUT0 IN0 IN0 FUNCTION Positive Supply Voltage. Bypass VCC to VGG with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to CLK. Inverting Differential Select Input Noninverting Differential Clock Input Inverting Differential Clock Input Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs. Setting EN = 0 and EN = 1 disables all four outputs. Inverting Differential Output Enable Input Noninverting Differential Input 3 Inverting Differential Input 3 Ground Reference Inverting Differential Output 3 Noninverting Differential Output 3 Negative Supply Voltage. Bypass from VEE to VGG with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Input 2 Inverting Differential Input 2 Inverting Differential Output 2 Noninverting Differential Output 2 Noninverting Differential Output 1 Inverting Differential Output 1 Inverting Differential Input 1 Noninverting Differential Input 1 Noninverting Differential Output 0 Inverting Differential Output 0 Inverting Differential Input 0 Noninverting Differential Input 0
MAX9424-MAX9427
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
Functional Diagram
VCC 1, 8 VCC 32 IN0 IN0 31 VGG D D CK VCC 26 IN1 IN1 25 VGG D D CK CK VCC 15 IN2 IN2 16 VGG 1 VCC 19 D D CK VCC 9 IN3 IN3 10 VGG D D CK VCC 4 CLK CLK 5 CK Q Q VEE 1 VCC 13 0 12 OUT3 OUT3 CK Q Q VEE 0 18 OUT2 OUT2 Q Q VEE 1 VCC 22 0 23 OUT1 OUT1 CK Q Q VEE 1 VCC 28 0 29 OUT0 OUT0 VGG 11, 17, 24, 30 VEE 14, 20, 21, 27
2 SEL SEL 3
MAX9424 MAX9425 MAX9426 MAX9427
6 EN EN 7
VGG
6
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
VCC VID VID = 0 VILD (MAX) VOH - VOL VIHD (MIN) VID VGG INPUT VOLTAGE DEFINITION (PECL) VID = 0 VILD (MIN) OUTPUT VOLTAGE DEFINITION (ECL) VEE VOCM VOL VOH VIHD (MAX) VGG
Figure 1. Input and Output Voltage Definitions
IN_ IN_ 100k IN_ IN_
MAX9424/MAX9425
MAX9426/MAX9427
VGG
VGG
50 OUT_ 50 OUT_
OUT_ OUT_ 8mA 8mA VEE
MAX9424/MAX9426
MAX9425/MAX9427
Figure 2. Input and Output Configurations
Detailed Description
The MAX9424-MAX9427 high-speed, low-skew PECL-toECL differential translators are designed for high-speed data and clock driver applications. These devices translate up to four PECL signals to ECL signals. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9424 has open inputs and open-emitter outputs. The MAX9425 has open inputs and 50 series outputs. The MAX9426 has 100 differential input impedance and open-emitter outputs. The MAX9427 has 100 differential input impedance and 50 series outputs.
Supply Voltages
These devices require a positive voltage supply (connect to VCC), a negative voltage supply (connect to VEE), and a ground reference (connect to VGG). VCC is independent of VEE and therefore the supply voltages do not need to be symmetrical. The PECL input voltages are referenced to VCC, and the ECL output voltages are referenced to VGG.
Data Inputs and Outputs
The input and output structures are shown in Figure 2. The open inputs of the MAX9424/MAX9425 require external termination, whereas the MAX9426/MAX9427 have integrated 100 differential input termination resistors between IN_ and IN_.
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
IN_ VIHD - VILD IN_
tPLH1 OUT_ VOH - VOL OUT_
tPHL1
80%
VOH - VOL
80%
OUT_ - OUT_
DIFFERENTIAL OUTPUT WAVEFORM
20%
VOH - VOL
20%
tR
tF SEL = HIGH EN = HIGH
Figure 3. IN to OUT Propagation Delay and Transition Timing Diagram
CLK VIHD - VILD CLK
tH IN_
tS
tH
VIHD - VILD IN_
tPLH2 OUT_ VIHD - VILD OUT_
tPHL2
SEL = LOW EN = HIGH
Figure 4. CLK to OUT Propagation Delay Timing Diagram
The MAX9425/MAX9427 have internal 50 series-output termination resistors and 8mA internal pulldown current sources, removing the need for external termination. The MAX9424/MAX9426 have open-emitter outputs, which require external termination (see the Output Termination section).
Asynchronous Operation
Setting SEL = high and SEL = low enables the four channels to operate independently. The clock signal is ignored in this mode. When asynchronous mode is selected, drive or bias the CLK and CLK inputs. Biasing the clock inputs properly is shown in Figure 5. This prevents the unused clock inputs from toggling, which eliminates unnecessary switching noise.
Enable
Setting EN = high and EN = low enables the device. Alternatively, setting EN = low and EN = high forces the outputs to a differential low; all changes on CLK, SEL, and IN_ are ignored.
8
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
VCC VCC
IN_ OUT_ 100 OUT_ IN_ 1k 1/4 MAX9424/MAX9425
IN_ OUT_ 100 OUT_ IN_ 1k 1/4 MAX9426/MAX9427
VGG
VGG
Figure 5. Input Bias Circuits for Unused Inputs
Synchronous Operation
Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode where the buffered inputs are clocked out simultaneously on the rising edge of the differential clock input (CLK and CLK). To have the input signals clocked out on the falling edge, swap the clock lines.
Power-Supply Bypassing
Typically, VGG is directly connected to ground. Bypass each VCC pin to VGG with high-frequency surface-mount ceramic 0.01F capacitors. Place these capacitors as close to the device as possible. Use the same bypass capacitor configuration between each VEE pin and VGG. In high-frequency, high-noise environments, add a 0.1F capacitor in parallel with each 0.01F capacitor. Use multiple vias when connecting the bypass capacitors to VGG (ground). This reduces trace inductance, lowering power-supply bounce when drawing high transient currents.
Differential Signal Input
The maximum input signal magnitude for each of the devices is VCC - VGG or 3.0V, whichever is less. This includes IN_, IN_, CLK, CLK, SEL, SEL, EN and EN.
Applications Information
Input Bias
Bias any unused inputs as shown in Figure 5. This avoids noise coupling that can cause toggling of the unused outputs.
Circuit Board Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners, and using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
Output Termination
Terminate the open-emitter outputs (MAX9424/ MAX9426) through 50 to VGG - 2V or use equivalent Thevenin terminations. Terminate both outputs of a differential pair and use identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT0 is used as a singleended output, terminate both OUT0 and OUT0. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device's total thermal limits should be observed.
Chip Information
TRANSISTOR COUNT: 882 PROCESS: Bipolar
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Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424-MAX9427
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
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Lowest Jitter Quad PECL-to-ECL Differential Translators
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
MAX9424-MAX9427
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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